In telecommunication systems, nodal equipment send and receive data from each other by way of a transmission network connecting the nodes. If the clock of the receiving circuit is not synchronised to the frequency and phase of the arriving data, the data can not be received correctly. The clock frequency of the receiving circuit is formed in almost all cases by a phase locked loop (PLL).
In the telecommunication industry there is a constant demand for phase locked loops PLL having different central frequencies and band widths. A long transmission distance results in a poorer received signal while a distorted input signal makes great demands on the clocks regeneration block. A phase locked loop where a data flow arriving from the network functions as the reference signal must be as immune as possible to any phase noise from the network and the phase noise generated by itself must be insignificant.
The phase lock must preserve the phase of the regenerated clocks in such a way that the decision-making point is at its optimum in the middle of the eye diagram of the arriving data flow. Secondly, in situations where a blackout occurs in the arriving data flow it must be able to maintain the frequency with moderate precision, and thirdly, in a situation where an interrupted data signal returns, the locking time of the phase lock must be as short as possible.
Several different integrated circuits may be used as oscillators for the phase lock. Suitable oscillators are e.g. a ring oscillator and a current controlled balanced relaxation oscillator.
Great demands are made on a PLL oscillator. It must
a) have a low phase noise PA1 b) the range of regulation should be large due to production tolerances, and PA1 c) the output frequency should be linearly dependent on the regulation voltage.
Production and assembly costs should also be low, and this is indeed a factor which restricts the complexity of the oscillator from an industrial point of view. These demands are partly contradictory: it is true that a large range of regulation is achieved with a big gain of the oscillator circuit, but at the cost of noise, and correspondingly a small gain will only produce a narrow range of regulation. In a locking state a big gain is required for the locking to take place quickly, but in a locked state a big gain will cause interfering phase noise. A small gain improves phase stability and reduces the noise caused by any signal that may have passed through the filter and that is of the same frequency as the phase reference signal.
The frequency range of an integrated monolithic voltage or current controlled oscillator is of an inexact nature and without any external components and structures affecting the frequency. However, it is not desirable to use any external structures, because, firstly, they add to the total surface area of the system and, secondly, they make the system less reliable.
A moderately exact free running frequency is necessary e.g. to ensure locking of the receiver of telecommunication equipment to the input signal. An exact frequency is also necessary for the reason that the static phase error of input signals to the PLL phase comparator should be as small as possible. A big difference between the input signal and the central frequency of the oscillator will bring about an asymmetric tracking range in the phase lock, whereby without any kind of tuning the integrated VCO is not able to track the frequency of the arriving signal, except only upwards or downwards.
Referring to the curves shown in FIG. 1, the oscillator's operation will also be illustrated. The figure shows with curves the output frequency of the oscillator as a function of the control voltage. Due to the decentralised production process it is not possible to know exactly beforehand which is the characteristic of the individual oscillator. For this reason, the characteristics form a family of curves, and when taking one individual integrated PLL, the only thing known is that the non-linear characteristic of the oscillator is some curve in the family of curves. When in the lower part of the voltage regulation range according to the curve, in the 1.5 V range in the figure, the output frequency changes very slowly and mostly non-linearly when the control voltage changes. In the 1.5V-3V range, the output frequency changes linearly as a function of the voltage and this range is in fact the range of regulation of the oscillator. After the linear range the frequency changes non-linearly. In the topmost curve the central frequency of the oscillator is e.g. f.sub.c and it is in the middle of the linear range at point C, that is, at control voltage 2.2V. On both sides of the central frequency in range .DELTA.f the operation is still linear. Together the ranges form the oscillator's range of regulation.
It is easy to see the difficulty in practice from the curves in the figure. When the PLL is locked and it produces frequency f.sub.0, it is impossible without measurements to know whether the operation is at point B of the lowest curve or at point A of the following curve. If the operation is at point A, the point of operation is close to the lower limit of the control voltage regulation range. When the input signal frequency changes and becomes slightly lower than frequency f.sub.0, the loop is no longer able to lock to the input signal.
FIGS. 2 and 3 show some known basic PLL solutions.
In a circuit according to FIG. 2, an oscillator is used, which has two control inputs, which are inputs IN1 and IN2 respectively. Hereby the control signal supplied by phase comparator 23 and filtered by loop filter 22 is taken to input IN1 and the signal supplied by frequency comparator 24 is taken to the other control input IN2 of oscillator 21. The lock is locked with the aid of the frequency comparator and a separate reference clock. After the locking, however, the effect of frequency comparator 24 must be eliminated, because the frequency of the reference clock and the DATA frequency of the input signal are not necessarily exactly the same.
The solution shown in FIG. 3 differs from the solution in FIG. 2 in that no external reference clock is used, whereby the frequency and phase comparator have the same input signals. This circuit requires a complex frequency comparator.
In each solution a problem occurs when the entire PLL is integrated. Hereby the oscillator's characteristic has a divergence as shown in FIG. 1, and it is not possible to know which curve belongs to the concerned oscillator. Hereby when putting the loop into use in some piece of equipment it may happen that the loop will lock but the control voltage is in fact at either side of its range of regulation and the input signals of the phase comparator may be far from their nominal phase difference.
It is an objective of the present invention to provide a PLL circuit especially suitable for integrated circuits which helps the loop to lock to the middle of the range of regulation and with which a sufficiently exact phasing is attained.
The established objective is achieved with a circuit the characteristics of which are presented in the independent claims.